CMOS and SET...

(a) SEM image of the e-beam patterned nanoelectrodes (scale bar 20 μm); inset: nanoelectrode structure with 12 nm gap. (b) Room temperature I-V measurements with drain voltage sweeping from 0.1 V to 0.7 V at gate voltage of -12.2V.

Topics: Nanotechnology, Photonics, Semiconductor Technology, Quantum Mechanics

As complementary metal-oxide semiconductor (CMOS) devices shrink to sub 5 nm, interference due to quantum size effects becomes unavoidable. Single-electron tunnelling (SET) devices provide a promising alternative for low-power integrated circuits due to their operation at the single electron level. Reporting in Nanotechnology, researchers aim to address this need by fabricating monodisperse ultra-small gold nanoparticles (AuNPs) deposited by a CMOS-compatible tilted-target sputtering technique.

Fabrication and integration of monodisperse ~1 nm metal nanoparticles as charge transport islands in a device configuration remains a major challenge in the progress of SET device technology. Here, the researchers deposit AuNPs into 12 nm nanogaps between electrodes, fabricated using high-resolution e-beam lithography. The ~1 nm AuNP functions as a charge transport island within a transistor configuration and the resultant device can explore the AuNP’s quantum coulomb blockade and quantized energy level spacings at room temperature (300 K).

Nanotechweb:

CMOS-Integrable room-temperature operational single-electron transistors

Haisheng Zheng is a PhD candidate supervised by Shubhra Gangopadhyay at the University of Missouri-Columbia in the department of Electrical and Computer Engineering.