...no, not him:
Image Credit: movie-squad.blogspot.com
...but, dare I say just as "impactful"?
Image Credit: Nature
Most transistors are 2D, or what makes up a transistor: source, drain and gate (that channels current when the right voltage is applied) all lie flat in the same plane. Intel's 3D uses the portruding "fin" resulting in three sides contacting the overlapping gate: Tri-Gate.
The concept was first introduced as the "FinFET" design by Dr. Chenming Hu and his colleagues at the University of California, Berkeley in the 90s. TSMC and Samsung are working on their own FinFET/Tri-Gate designs.
Currently, Polysilicon gates are in the range of 22 - 35 nanometers (10 to the minus 9 meters, or 0.000000001 meters). This will drive the technology to 14 nanometers or smaller and transistor speeds should be 37% faster.
The smaller we get, the more defectivity (I was a once a product/yield enhancement engineer) plays into manufacturing as well as quality concerns: the slightest amount of dirt will short out circuits the size of atoms. The smaller we go, quantum effects will come into play.
But that is the challenge... and the opportunity.
"Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction."
"It's not that I'm so smart, it's just that I stay with problems longer."
Both quotes by Albert Einstein
Link to article: Intel enters the third dimension
No comments:
Post a Comment